CONCURRENCY MODEL FOR NETWORK-ON-CHIP DESIGN ARCHITECTURE

A. Agarwal∗ and R. Shankar∗

References

  1. [1] G. Desoli & E. Filippi, An outlook on the evolution of mobile terminals: From monolithic to modular multi-radio, multiapplication platforms, IEEE Magazine CAS, 6(2), 2006, 17–29.
  2. [2] J. Ahmed Meine & W. Wayne, Multiprocessor system-on-chips (Amsterdam, Boston, London, New York, Tokyo: Morgan Kaufamann Publisher, 2005).
  3. [3] L. Benini & G.D. Micheli, Networks on chip: A new SOC paradigm, IEEE Computer, 35(1), 2002, 70–78.
  4. [4] A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. ¨Oberg, M. Millberg, & D. Lindqvist, Network on chip: An architecture for billion transistor era, Proc. of IEEE NorChip Conference, 2000, 8–12.
  5. [5] D. Bertozzi & L. Benini, Xpipes: A network-on-chip architecture for gigascale system-on-chip, IEEE Circuits and Systems, 4(1), 2004, 18–31.
  6. [6] E. Cota, M. Kreutz, C.A. Zeferino, L. Carro, M. Lubaszewski, & A. Susin, The impact of NoC reuse on the testing of core-based systems, 21st Proceedings of VLSI, 2003, 128–133.
  7. [7] A. Jantsch & H. Tenhunen. Networks on Chip (Boston, Dordrecht, London: Kluwer Academic Publisher, 2003).
  8. [8] S. Kumar, A. Jantsch, J-P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, & A. Hemani, A network on chip architecture and design methodology, IEEE Computer Society Annual Symposium on VLSI, 2002, 117–124.
  9. [9] X. Jiang, W. Wolf, J. Hankel, & S. Charkdhar, A methodology for design, modelling and analysis for networks-on-chip, IEEE International Symposium on Circuits and Systems, 2005, 1778– 1781.
  10. [10] A. Agarwal & R. Shankar, A layered architecture for NOC design methodology, IASTED ICPDCS, 2005, 659–666.
  11. [11] P.P. Pande, C. Grecu, M. Jones, A. Ivanov, & R. Saleh, Performance evaluation and design trade-offs for network-on-chip interconnect architectures, IEEE Transactions on Computers, 54(8), 2005, 1025–1040.
  12. [12] Semiconductor Industry Association, The international technology roadmap for semiconductors (ITRS) 2001, http://public.itrs.net/Files/2001ITRS/Home.htm.
  13. [13] H. Sutter, The free lunch is over: A fundamental turn toward concurrency in software, Dr. Dobb’s Journal, 30(3), 2005.
  14. [14] D.R. Butenhof, Programming with POSIX threads, (Boston, London, Paris, New York: Addition-Wesley, 1997).
  15. [15] M. Guler, S. Clements, N. Kejriwal, L. Wills, B. Heck, & B.G. Vachtsevanos, Rapid prototyping of transition management code for reconfigurable control systems, 13th IEEE International Workshop on Rapid System Prototyping, 2002, 76–83.
  16. [16] J. Burch, R. Passerone, & A.L. Sangiovanni-Vincentelli, Overcoming heterophobia: modelling concurrency in heterogeneous systems, IEEE International Conference on Application of Concurrency to System Design, 2001, 13–32.
  17. [17] G.H. Hilderink, Graphical modelling language for specifying concurrency based on CSP, IEEE Proceedings on Software Engineering, 150(2), 2003, 108–120.
  18. [18] S. Chrobot, Modelling communication in distributed systems, IEEE International Proceeding in Parallel Computing in Electrical Engineering, 2002, 55–60 246
  19. [19] T. Murphy, K. Crary, R. Harper, & F. Pfenning, A symmetric modal lambda calculus for distributed computing, Annual IEEE Symposium on Logic in Computer Science, 2004, 286–295
  20. [20] A. Girault, B. Lee, & E.A. Lee, Hierarchical finite state machines with multiple concurrency models, IEEE Transaction on CAD of Integrated Circuits and Systems, 18(6), 1999, 742–760.
  21. [21] M. Barrio & P.D.L. Fuente, A Formal Model of Concurrency for Distributed Object-Oriented Systems, IEEE International Computer Science Conference on Software Engineering, 1997, 466–474.
  22. [22] D. Sangiorgi., Expressing mobility in process algebras: Firstorder and higher-order paradigms. Ph.D. thesis, Computer Science Department, University of Edinburgh, May 1993.
  23. [23] V.D. Bianco, L. Lavazza, & M. Mauri, Model checking UML specifications of real time software, 8th IEEE International Conference on Complex Computer Systems, 2002, 203–212.
  24. [24] J. Magee & J. Kramer, Concurrency state models and Java programs, (West Sussex England: John Wiley & Sons, 1999).

Important Links:

Go Back