CONCURRENCY MODEL FOR NETWORK-ON-CHIP DESIGN ARCHITECTURE

A. Agarwal∗ and R. Shankar∗

Keywords

Concurrency modelling, networkonchip architecture

Abstract

Designers exploit design reuse to enhance system design productivity. Integration of pre-designed reusable blocks may fail if these blocks execute in parallel, share resources, and/or interact with each other. Such concurrency issues, if not addressed, may be detrimental to normal functioning of the system. Multiprocessor architectures, recently introduced to extend the applicability of the Moore’s law, depend upon concurrency and synchronization in both software and hardware to achieve that goal. Concurrency issues, if not addressed, may lead the system into a deadlock or a livelock state. System design integration and verification approaches will not be cost-effective in exposing concurrency failures as they are intermittent; this can be costly (significantly increased time to market and field failures). One would have to develop abstract concurrency models and do exhaustive analysis on these models to test for concurrency problems. In this paper we present a systematic approach that models concurrency by using an abstract symbolic modelling language to build a systematic high level concurrent system model; we also use an exhaustive analysis and verification tool to confirm that the system is devoid of concurrency failures. We present results for the NOC (network-on-chip) multiprocessor platform.

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