Y. Kanazawa, T. Asai, M. Ikebe, and Y. Amemiya
Dynamic synapse, depressing synapse, spiking neuron, analog circuit, neuromorphic VLSI
A compact complementary metal-oxide semiconductor (CMOS) circuit for depressing synapses is designed for demonstrating applications of spiking neural networks for contrast-invariant pattern classification and synchrony detection. Although the unit circuit consists of only five minimum-sized transistors, they emulate fundamental properties of depressing synapses. The results of the operations are evaluated by both experiments and the simulation program with integrated circuit emphasis (SPICE).
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