D. Orui, S. Tsukiyama, and I. Shirakawa (Japan)
Interconnect delay, estimating method, RC tree, ramp input, and fidelity
The first step of interconnect design for a multi-terminal net is interconnect topology design, in which an efficient and high fidelity estimation method of interconnect delays is indispensable, because if the estimation method does not have fidelity, we may misjudge in selecting an optimal topology for the net which minimizes the interconnect delay. In this paper, we propose a new interconnect delay estimation method for an RC tree, which increases the fidelity from the previous methods and can treat a saturated ramp input. The method uses the first three moments of input admittance and the first two moments of transfer function, and solves the voltage waveform at a node by using RC 2 ladder circuit. In order to see the performance of the proposed method, we show some experimental results, which demonstrate that the variation of the absolute values of relative errors of estimated delays are reduced from the previous methods.
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