M.C. Wang (USA)
D-latch, CMOS, VLSI, memory, architecture.
On-chip memories, such as D-latch, form cores of many digital applications. Two back-to-back D-latches with opposite clock phase form a flip-flop, which is used in every synchronous digital system. Therefore, any improvement in performance of D-latch will translate to improvement in performance of the entire chip. In this paper, we propose and investigate a novel 7-Transistor D latch cell that has numerous advantages over its conventional counterparts. HSPICE simulation shows that compared to the conventional 8T transmission gate D latch, the proposed 7T D-latch has on average 19% power consumption reduction and 22% area reduction at the cost of 15% increase in delay.
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