M.C. Wang and S.-E. Wang (USA)
SRAM, CMOS, VLSI, memory, architecture
On-chip memories, such as static random access memory (SRAM), form cores of many digital applications. SRAMs are commonly used as caches in microprocessors, as well as look-up tables in field programmable gateway array (FPGA). As technology scaling continues, SRAMs are required to be fast, small, stable, and power efficient – all qualities are difficult to achieve simultaneously. In this paper, we propose and investigate a novel 7-transistor SRAM that achieves read and write stability by utilizing different word lines and only single bit line. HSPICE simulation shows that the proposed single bit line 7T SRAM has 198% read margin improvement, 33% write margin improvement, 47% power consumption reduction and 19% cell area reduction over the conventional 6T SRAM, at the cost of 56% increase in access time.
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