An Evolutionary Time-Series Model for Partitioning a Circuit Pertaining to VLSI Design using Neuro-Memetic Algorithm

K.A. Sumitra Devi, N.P. Banashree, and A. Abraham (India)


VLSI, Circuit Partitioning, Neuro-Memetic, Memetic algorithm


This paper proposes a superior approach to solve problem of circuit Partitioning. It presents a scaffold for a statis tical glitch prediction system using a Neuro-Memetic model, which predicts to divide the circuit into a number of sub-circuits with minimum interconnections between them. In this paper, we propose an evolutionary time series model for partitioning a circuit using neuro Memetic algorithm owing to its local search capability. The experimental results show that the combination strategy (Neuro-Memetic) can quicken the learning speed of the network and improve the predicting precision compared to memetic approach. A comparative study is provided using the two machine learning approaches using memetic and Neuro-memetic to solve the problem of circuit partitioning pertaining to VLSI design. The performance of both approaches is compared using benchmark data provided by MCNC standard cell placement benchmark netlists. Analysis of the investigational results proved that the Neuro-memetic model achieves greater performance then memetic approach in recognizing sub-circuits with lowest amount of interconnections between them.

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