VLSI Design of Iterative Karatsuba Multiplier and Its Evaluation

S. Yazaki and K. Abe (Japan)


multi-digit multiplication, Karatsuba, VLSI, performance, area cost, energy consumption


Multi-digit multiplication is widely used for various ap plications in recent years, including numerical calculation, chaos arithmetic, primality testing. Systems with high per formance and low energy consumption are demanded, es pecially for image processing and communications with cryptography using chaos. In this paper, hardware design of multi-digit integer multiplication is described and its VLSI realization is evaluated in terms of the cost and per formance. A version of Karatsuba hardware using 0.18µm process can perform 512-bit multiplications 30 times faster than software at the area cost of 6.91mm2 . Computation energy was found to be nearly 10−3 of that consumed by general purpose processor which executes the software ver sion . The results obtained by this study will help system designers for applications requiring multi-digit multiplica tion to select design alternatives including ASIC realiza tion.

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