Analysis of Bit Error Rate for Interconnect Pipelining

J. Xu and M.H. Chowdhury (USA)


Interconnect Pipelining, Statistical Timing Analysis


As integrated circuits technology enters into interconnect centric nanometer regime, it will be impossible to carry cross-chip signals in a single clock cycle and interconnect pipelining becomes an acceptable solution beyond traditional buffer-insertion based interconnect systems. This paper performed a detailed analysis for the bit error rate (BER) in the two interconnect pipelining approaches, and find that the BER is unusually high for some cases. Here, we discussed the best position for the inserted sequential elements and analyzed the cause of the high BER. Then, a method to deal with the high BER is proposed. A comparative study of the two interconnect pipelining approaches is also presented in this paper, which will help exploring trade-offs between number of sequential elements inserted and the probability of bit error during data transmission.

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