An Efficient 2-D DWT Architecture with Reduced Memory Accesses for Low Energy Consumption

N. Ishihara and K. Abe (Japan)


DWT, low energy consumption, efficient memory access, line-based, data flow, ASIC


Discrete Wavelet Transform (DWT) has been widely used for multimedia processing such as signal analysis, signal compression, and numerical analysis, and there has been an increase of research into the hardware architecture of 2 D DWT for applications in intelligent environments such as mobile communications. However, because of its complex data flow and intensive arithmetic computation, designing an efficient 2-D DWT architecture with high throughput and small size internal memory for low energy consump tion is a challenge. In this paper, we propose a new 2 D DWT architecture. To reduce energy consumption, we focus on the number of memory accesses which consume dominant part of total energy. The proposed method im proves data flow of line-based architecture to reduce the number of internal memory accesses. In addition, we mod ify external memory allocation so that a port width of ex ternal memory is fully utilized. We also modify wavelet filter to align memory word segments with coefficients to be loaded. Evaluation results indicate that proposed archi tecture reduces both external and internal memory accesses resulting in low energy consumption.

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