C.-H. Kuo, S.-C. Chen, and K.-S. Chang (Taiwan)
Analog-to-digital converters, delta-sigma modulators, low-voltage, switched-opamp, switched-capacitor circuits
In this paper, a low-voltage switched-opamp-based 2-2 cascaded switched-capacitor delta-sigma modulator in a 0.18-µm 1P6M CMOS technology is presented. The fourth-order modulator is realized using a low-distortion feed-forward topology to promote its linearity and dynamic range. The presented modulator can be operated in a wide range of supply voltage from 1.8V to 0.9V. The switched-opamp with double output stage is utilized to combine with the double-sampling technique so that the effective clocking rate can be reduced, thus also relaxing the requirement of opamp. The modulator achieves a 91 dB of SNDR within 24 kHz signal bandwidth under a 2 MHz of clocking rate. The total power consumption of this modulator is 0.86 mW under a 1V supply voltage and the chip core area is 1.57mm2 .
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