H. Durmus, A. Joshi, and J. Choma, Jr. (USA)
Converters, imaging, delta-sigma, high resolution
This paper introduces resettable higher-order ∆-Σ (Delta Sigma) analog-to-digital converters (ADCs) suitable for imaging applications. Higher order ∆-Σ converters were not preferred in imagers for several reasons: Stabilizing a high order system is difficult and is usually achieved by keeping the input swing much smaller than the reference. Secondly, decimation filter is bulky and history of previous samples within the decimation filter causes correlation among successive data. In this work, residue from previous samples is cleared by resetting the converter for each input while maintaining a higher order converter. Stability and full input swing is ensured through local comparator decisions at each stage. As a result low oversampling ratio (OSR) and high resolution ∆-Σ converters can be used in imagers effectively. The converter topologies have very simple, power and area efficient digital decimation filters that are also reset for each input. When several resettable higher order ∆-Σ converters are used in parallel, very high-resolution high output-rate sensor arrays can be realized. Simulation results of a 4th order resettable ∆-Σ converter shows that 16 bits of resolution is achieved with 30mW of power dissipation at output sample rates of 1MSPS.
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