S.H. Chang, D.W. Cheun, T.K. Yu, and S.D. Kim (Korea)
System-on-Chip (SoC), Product Line Engineering (PLE), Software Reuse
System-on-Chip (SoC) technology enables implementing a fairly complex functionality in a small form-factor, and hence SoC becomes a key component of embedded systems. With the advances of semiconductor technology, the amount of functional features that a single SoC can embed increases sharply. Accordingly, the time and cost for developing SoCs are also increasing. A fundamental solution to manage the complexity is reuse engineering. Intellectual Property (IP) is a representative reuse approach; however, the reusability with IPs is limited to a relatively small grained functionality. As an effective reuse approach, product line engineering (PLE) is to capture common features among products into a core asset and to instantiate it for target products. In this paper, we propose a PLE-based process for designing SoC. Our process is centered on modeling variability as well as commonality among a family of SoCs. Using the proposed process, SoCs can cost effectively developed.
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