A Parallel Sort Engine with Dynamic Memory for a Multiprocessor-on-a-Chip

N. Tabrizi and N. Bagherzadeh (USA)


ASIC design, dynamic memory cells, network-on-a-chip, sorting accelerator, VLSI.


: We propose a custom-designed alternative to a memory system (generated by a memory generator) used in a 4K-word sorting accelerator which improves area efficiency by some 20%. We also show how the control unit is dramatically simplified with this new memory comparing with the sophisticated memory controller in the previous version. Furthermore, since the memory introduced here is custom designed, its size is tailored to any specific need.

Important Links:

Go Back