Effects of Input Variations in Interconnection Trees

R. Sharma (India)


Delay, rise time, settling time, VLSI circuit and systems.


In this work, we establish the effects of changes in input excitations on delay parameters. In that we consider 50% propagation delay, rise time and %5± settling time using lumped RLC tree model. We have taken a more practical class of inputs, such as ramp and exponential input excitations apart from step input. It has been found analytically that as the input deviates from ideal step the delay parameters are severely affected, but settling time remains almost the same. Also, the results establish the fact that ramp input excitation can be used as an approximation to exponential input without much compromise on actual delay values.

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