Design Issues and Implementation Strategies for Building On-Chip Voltage Level-Shifting Circuits

P. Lakshmikanthan and A. Nuñez (USA)

Keywords

Circuit Design, DC-DC Voltage Conversion, On-Chip Level Conversion

Abstract

Present process technologies (180 nm and below) oper ate at supply voltages below 1.8V. The power requirements of high-performance chips designed using these technolo gies is in range of 70-100W. Shrinking supply voltages (≤ 1.8V) imply extremely high currents (50-90 amps) flow ing through the chip. Being able to step up and step down the voltage when required in the chip, greatly reduces the current flowing through the sensitive circuits. This up and down voltage conversion is achieved through the use of DC-DC level conversion circuits. This paper describes the design issues faced and corresponding implementation strategies followed in designing up and down on-chip DC DC voltage level shifter circuits. An experimental ripple carry adder circuit working at different voltage levels using level shifting circuits is presented.

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