Clock-Tree Synthesis for EMC-Aware Design

D. Pandini and G.A. Repetto (Italy)


Electromagnetic compatibility (EMC), electromagnetic interference (EMI), EMC-aware design, clock distribution, clock-tree synthesis (CTS).


In modern electronic products, like microprocessors, consumer electronics, and networking applications, the increasing demand for performance and throughput requires higher operating frequencies in the order of hundreds of megahertz, and in several cases exceeding the gigahertz range. With the present and future technology scaling trends, this request will continue to rise. With such working frequency increment, there often is an increase in electromagnetic interference (EMI). The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMI and radiated emissions are rapidly becoming a major problem for high-speed circuit and package designers. Among the most detrimental sources of EM emissions there are the on-chip clock and data signals with fast rise/fall edges, and a large high frequency spectral content. In this work, we propose an effective and practical methodology for EMC-aware clock-tree synthesis, which globally reduces the high-frequency harmonics of the clock waveforms by increasing the clock rise/fall times, while preserving the functionality of the system.

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