A. Vaidyanathan, A. Varde, S. Iyengar, S. Settikeri, and S. Subramaniam (USA)
Engineering Change Order, Design Synthesis Tool, Automatic Placement and Routing, Clock Tree Synthesis
Implementing Engineering Change Orders (ECOs) using only spare gates and metal masks is part of every designer’s job. With a Register Transfer Logic (RTL) design methodology, if RTL synthesis tools were used for development of the original design, it becomes very cumbersome to track the RTL changes to the gate-level netlist. This paper will discuss a new approach for developing tools to implement complex ECOs with minimal designer interference. A semi-automated technique to implement an ECO through automatic iterative constraining of RTL synthesis and Automatic Placement and Routing (APR) tools will be presented. The paper will show how, while designer intervention may not be reduced to zero, it is significantly less when compared to all-manual methods.
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