H. Ishijima, K. Kusano, T. Harada, Y. Kawakami, and M. Fukui (Japan)
Power and ground routing, power grid, IR-drop, electro migration
This paper presents a new optimization technique to design a power grid network of an LSI chip, which considers wiring congestion, power supply voltage drop, inductance noise influence at power pads, and electro migration risk simultaneously. In conventional approach, the factors are optimized on multi-state. However, this algorithm implemented the multi-objective optimization on single-state. The single-state optimization is more efficient than the multi-state optimization. We have examined this new approach for practical examples and get feasible solutions from unfeasible starting points. Also, we have got a good scope for its computation time to be efficient for large examples. The experimental results show that three risks we have defined are well improved; moreover IR-drop, electro-migration and wiring congestion are optimized. We have obtained a feasible solution with a small computational time, compared with our old approach.
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