H.-C. Chow and C.-H. Su (Taiwan)
All-digital phase-locked loop, low power, low jitter, and digitally-controlled oscillator
A new method is proposed in the paper, to accomplish the fine tune unit of the digital controlled oscillator of an all digital phase-locked loop (ADPLL). Instead of using adjustable currents, we utilize the difference of the equivalent capacitance obtained from the drain of MOS transistors between on and off conditions as the fine tune delay parameter. Based on post-layout simulation results, the time resolution of the fine tune delay element including parasitic capacitances, can achieve 1.7126 ps. The operating frequency range of this presented ADPLL is between 308 MHz and 587 MHz. As compared to prior arts, the power consumption per MHz is improved by 15% and the jitter is less than 5 ps, which has a significant improvement.
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