C. Zheng and J.R. Heath (USA)
Single-chip multiprocessor architecture, modeling, simulation and visualization.
A single-chip, hybrid, heterogeneous, and dynamic (reconfigurable) shared memory multiprocessor architecture is being developed. The architecture executes real or non real-time applications described by dataflow (process flow) graphs of any topology. It can dynamically reallocate computational resources and reconfigure its structure at the node and processor architecture levels to maximize performance and to increase reliability and fault tolerance. The architecture is a Hybrid Data/Command Driven Architecture (HDCA). It operates as a dataflow architecture at the process level. The contribution of this manuscript is its focus on the development, testing and evaluation of a new simulation and visualization graphic software (hdca). The software first performs application mapping and static resource allocation for a HDCA in a manner to meet application timing requirements. Next, hdca simulates the architecture executing the application using statically assigned resources and parameters. While simulating the architecture, the software graphically and dynamically visually displays functionality, parameters and mechanisms within the architecture important to the architectures operation, control and performance. For the HDCA, the new graphical software allows visual evaluation of the effectiveness of utilized static and dynamic resource allocation, control and load balancing strategies, policies, procedures and algorithms. The hdca software can also collect and store specified HDCA operational and performance data for post simulation analysis and evaluation.
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