Power Flow Analysis on an FPGA-based Vector Computer

M.Z. Hasan (USA), S.G. Ziavras (USA/Korea), and T.-G. Chang (Korea)


Power flow, sparse matrix, vector computer, FPGA


The solution to a set of linear equations given in the form Ax = b, where A is an n×n sparse matrix and b is an n element vector, can be obtained with the W-matrix method for power flow studies. The characteristics of this method are explored here for sparse linear systems present in such studies and an enhanced vector processor is proposed to support them directly in hardware. The effects of customized instructions, instruction chaining, and matrix density are evaluated. The impact of multiple pipelined functional units, multiple data buses, and vector register size is analyzed as well. Our implementation of the vector processor on an FPGA (Field-Programmable Gate Array) is discussed and benchmark results are presented.

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