A VLSI Array Architecture for Artificial Neural Networks

L. Bengtsson (Sweden)

Keywords

: VLSI array architecture, Artificial NeuralNetworks, Backpropagation, SelfOrganizingFeatureMaps.

Abstract

. A highly parallel array architecture for ANN algorithms is presented and evaluated. The array, consisting of PEs inter connected as a 2D-grid, executes instructions according to the SIMD (Single Instruction Multiple Data) parallel computing model. The architecture is scalable, both in terms of problem size and when porting it to future down-scaled CMOS proc esses. As typical ANN examples, the feed-forward net with back-propagation training, and the Kohonen Self Organizing Feature Map are used. Performance metrics such as Connec tion-Updates-Per-Second (CUPS) and Connections-Per-Sec ond (CPS) are derived based on test implementations. A VLSI test chip design is presented in order to show the feasibility of implementing the architecture.

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