Shiyamala Subramani and Rajamani Vayanaperumal
MAP decoder, memory management, Zig-Zag algorithm, state metric, gate count
A modified architecture for the efficient memory management in MAP decoder based on Zig-Zag algorithm is proposed in this paper. Reducing memory elements is one of the method to achieve a low power in the turbo coder. State metric and path metric units consume large memory elements in the MAP decoder design. Single RAM can be used to store the metrics instead of two RAM by using Zig-Zag algorithm. Total gate count achieved based on Zig-Zag algorithm for the entire architecture is 11,708 for K = 5, rate = 1/2.
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