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MULTIPROCESSOR SYSTEMS AUTO-DESIGN FOR MULTIPLE USE-CASE APPLICATIONS ON FPGA
Da Li and Yibin Hou
References
[1] W. Wolf, The future of multiprocessor systems-on-chips, Proc.of 41st Annual Conf. on Design Automation, San Diego, CA,United states, 2004, 681–684.
[2] T. Agerwala and S. Chatterijee, Computer architecture: Chal-lenges and opportunities for the next decade, IEEE Micro,25(3), 2005, 58–69.
[3] S. Sriram and S. Bhattacharyya, Embedded multiproces-sors: Scheduling and synchronization (New York, NY: MarcelDekker, 2000).
[4] H. Nikolov, T. Stefanov, and E. Deprettere, Multi-processorsystem design with ESPAM, Proc. of the 4th Int. Workshopon Hardware/Software Codesign, Seoul, Korea, 2006, 211–216.
[5] A. Kumar, A. Hansson, J. Huisken, and H. Corporaal, AnFPGA design flow for reconfigurable network-based multi-processor systems on chip, Proc. of the Design Automationand Test in Europe, Nice, France, 2007, 117–122.
[6] K. Akash, F. Shakith, H. Yajun, M. Bart, and C. Henk,Multiprocessor systems synthesis for multiple use-cases ofmultiple applications on FPGA, ACM Transactions on DesignAutomation of Electronic Systems, 13(3), 2008, 1–27.
[7] V.R.L. Shen, A PN-based approach to the high-level synthesisof digital systems, Integration, the VLSI Journal, 39(3), 2006,182–204.
[8] W. Naiqi, B. Liping, and C. Chengbin, Modeling and conflictdetection of crude oil operations for refinery process basedon controlled colored timed Petri net, IEEE Transactionson Systems, Man and Cybernetics Part C: Applications andReviews, 37(4), 2007, 461–472.
[9] J.M. Paul, D.E. Thomas, and A. Bobrek, A scenario-orienteddesign for single-chip heterogeneous multiprocessors, IEEETransactions on Very Large Scale Integration (VLSI) Systems,14(8), 2006, 868–880.
[10] S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G.Micheli, A methodology for mapping multiple use-cases ontonetworks on chips, Proc. Design Automation and Test inEurope, Munich, Germany, 2006, 118–123.
[11] K. Jensen, L.M. Kristensen, and L. Wells, Coloured Petri netsand CPN tools for modelling and validation of concurrent sys-tems, International Journal on Software Tools for TechnologyTransfer, 9(3–4), 2007, 213–254.
[12] M. Westergaard and L.M. Kristensen, The access/CPN frame-work: A tool for interacting with the CPN tools simulator,Proc. 30th Int. Conf. on Applications and Theory of PetriNets, Paris, France, 2009, 313–322.
[13] S. Dutta, R. Jensen, and A. Rieckmann, Viper: A multipro-cessor SOC for advanced set-top box and digital TV systems,IEEE Design and Test of Computers, 18(5), 2001, 21–31.
[14] S. Pasricha, N. Dutt, and F.J. Kurdahi, Dynamically reconfig-urable on-chip communication architectures for multi use-case112chip multiprocessor applications, Proc. Design AutomationConf., Yokohama, Japan, 2009, 25–30.
[15] S. Stuijk, M. Geilen, and T. Basten, SDF3: SDF for free,Proc. 6th Int. Conf. on Application of Concurrency to SystemDesign, Los Alamitos, CA, United states, 2006, 276–278.
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Abstract
DOI:
10.2316/Journal.202.2013.3.202-3529
From Journal
(202) International Journal of Computers and Applications - 2013
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