Yuet M. Lam


  1. [1] T.C. Hu, Parallel sequencing and assembly line problems, Operations Research, 9(6), 1961, 841–848.
  2. [2] K.R. Pattipati, T. Kurien, R.T. Lee, and P.B. Luh, On mapping a tracking algorithm onto parallel processors, IEEE Transactions on Aerospace and Electronic Systems, 26(5), 1990, 774–791.
  3. [3] T. Pop, P. Eles, and Z. Peng, Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems, Proc. 10th International Symposium on Hardware/software Codesign, 2002, 187–192.
  4. [4] Y. Shin and K. Choi, Enforcing schedulability of multi-task systems by hardware-software codesign, Proc. Fifth International Workshop on Hardware/Software Codesign, 1997, 3–7.
  5. [5] Y. Guo, C. Hoede, and G. Smit, A pattern selection algorithm for multi-pattern scheduling, Proc. Parallel and Distributed Processing Symposium, 2006, 25–29.
  6. [6] I. Ahmad, M.K. Khodhi, and R. UI-Mustafa, DPS: Dynamic priority scheduling heuristic for heterogeneous computing systems, IEE Proceedings of Computers and Digital Techniques, 145(6), 1998, 411–418.
  7. [7] G.C. Sih and E.A. Lee, A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architecture, IEEE Transactions on Parallel and Distributed Systems, 4(2), 1993, 175–187.
  8. [8] H. Topcuoglu, S. Hariri, and M.Y. Wu, Performance-effective and low-complexity task scheduling for heterogeneous computing, IEEE Transactions on Parallel and Distributed Systems, 13(3), 2002, 260–274.
  9. [9] M. Hosseinzadeh and H.S. Shahhoseini, Earliest starting and finishing time duplication-based algorithm, Proc. International Symposium on Performance Evaluation of Computer and Telecommunication Systems, 2009, 49–56.
  10. [10] D. Bozdağ, F. Özgüner, and U.V. Catalyurek, Compaction of schedules and a two-stage approach for duplication-based DAG scheduling, IEEE Transactions on Parallel and Distributed Systems, 20(6), 2009, 857–871.
  11. [11] A. Bednarski and C. Kessler, Integer linear programming versus dynamic programming for optimal integrated VLIW code generation, Proc. 12th International Workshop on Compilers for Parallel Computers, 2006, 73–85.
  12. [12] S.O.M.F. Redaelli and M.D. Santambrogio, An ILP formulation for the task graph scheduling problem tailored to bi-dimensional reconfigurable, Proc. International Conference on Reconfigurable Computing and FPGAs, 2008, 97–102.
  13. [13] R. Cordone, F. Redaelli, M.A. Redaelli, M.D. Santambrogio, and D. Sciuto, Partitioning and scheduling of task graphs on partially dynamically reconfigurable FPGAs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 28(5), 2009, 662–675.
  14. [14] M.M. Rahman and M.F.I. Chowdhury, Examining branch and bound strategy on multiprocessor task scheduling, Proc. International Conference on Computer and Information Technology, 2009, 162–167.
  15. [15] L. Yang, T. Gohad, P. Ghosh, D. Sinha, A. Sen, and A. Richa, Resource mapping and scheduling for heterogeneous network processor systems, Proc. IEEE International Symposium on Architecture for Networking and Communications Systems, 2005, 19–28.
  16. [16] C.H. Papadimitriou and K. Steiglitz, Combinatorial optimization: Algorithms and complexity (Mineola, NY, USA: Dover Publications, 1998).
  17. [17] J.I. Hidalgo and J. Lanchares, Functional partitioning for hardware–software codesign using genetic algorithms, Proc. 23rd EUROMICRO Conference on New Frontiers of Information Technology, 1997, 631–638.
  18. [18] T. Wiangtong, P.Y.K. Cheung, and W. Luk, Hardware/software codesign: A systematic approach targetingdata-intensive applications, IEEE Signal Processing Magazine, 22(3), 2005, 14–22.
  19. [19] L. Shang, R.P. Dick, and N.K. Jha, SLOPES: Hardware-software cosynthesis of low-power real-time distributed embedded systems with dynamically reconfigurable FPGAs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(3), 2007, 508–526.
  20. [20] Y.M. Lam, J.G.F. Coutinho, W. Luk, and P.H.W. Leong, Integrated hardware/software codesign for heterogeneous computing systems, Proc. IEEE IV Southern Programmable Logic Conference, 2008, 217–220.
  21. [21] Y.M. Lam, J.G.F. Coutinho, W. Luk, and P.H.W. Leong, Mapping and scheduling with task clustering for heterogeneous computing systems, Proc. International Conference on Field Programmable Logic and Applications (FPL), 2008, 275–280.
  22. [22] Y.W. Wong, R.S.M. Goh, S.H. Kuo, and M.Y.H. Low, A tabu search for the heterogeneous DAG scheduling problem, Proc. International Conference on Parallel and Distributed Systems, 2009, 663–670.
  23. [23] S. Gupta and G. Agarwal, Task scheduling in multiprocessor system using genetic algorithm, Proc. Second International Conference on Machine Learning and Computing, 2010, 267– 271.
  24. [24] T.D. Braun, H.J. Siegel, N. Beck, L.L. Bölöni, M. Maheswaran, A.I. Reuther, J.P. Robertson, M.D. Theys, and B. Yao, A comparison of eleven static heuristics for mapping a class of independent tasks onto heterogeneous distributed computing systems, Journal of Parallel and Distributed Computering, 61, 2001, 810–837.
  25. [25] T. Wiangtong, P.Y.K. Cheung, and W. Luk, Comparing three heuristic search methods for functional partitioning in hardware–software codesign, Journal on Design Automation for Embedded Systems, 6(4), 2002, 425–449.
  26. [26] S.K. Mitra, Digital signal processing: A computer-based approach (NY, USA: McGraw-Hill, 2002).
  27. [27] A. Brace, D. Gątarek, and M. Musiela, The market model of interest rate dynamics, Mathematical Finance, 7(2), 1997, 127–155.

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