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EFFICIENT SYSTOLIC ARCHITECTURE FOR VLSI REALIZATION OF 2-D HARTLEY-LIKE TRANSFORM
Gouri S. Maharana, Pramod K. Meher, and Basant K. Mohanty
References
[1] R.N. Bracewell, Discrete Hartley transform, Journal of the Optical Society of America, 73(12), 1983, 1832–1835.
[2] R. Bracewell, The fast Hartley transform, Proceedings of the IEEE, 72(8), 1984, 1010–1018.
[3] J.G. Proakis and D.G. Manolakis, Digital signal processing: Principles, algorithms and applications (Upper Saddle River, NJ: Prentice-Hall, 1996).
[4] A. Bernardi and R.N. Bracewell, Updating the power spectrum of real data by the Hartley method, Proceedings of the IEEE, 75(7), 1987, 964–965.
[5] C.L. Wang, C.H. Chang, J.L. Fan, and J.M. Cioﬃ, Discrete Hartley transform based multicarrier modulation, Proc. IEEE International Conf. on Acoustics, Speech, and Signal Processing, Turkey, 5, May 2000, 2513–2516.
[6] J. Wu and J. Shiu, Discrete Hartley transform in error control coding, IEEE Transactions on Signal Processing, 39(10), 1991, 2356–2359.
[7] P.K. Meher and G. Panda, Unconstrained Hartley domain least mean square adaptive ﬁlter, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 40(9), 1993, 582–585.
[8] P.K. Meher and G. Panda, Fast computation of circular convolution of real-valued data using prime factor fast Hartley transform algorithm, Journal of IETE, 41, 1995, 261–264.
[9] C.L. Wang and C.H. Chang, A DHT-based FFT/IFFT processor for VDSL transceivers, in Proc. 2001 IEEE International Conf. on Acoustics, Speech, and Signal Processing, 2, USA, May 2001, 1213–1216.
[10] G. Maharana and P.K. Meher, Parallel algorithms and systolic architectures for 1- and 2-D interpolation using discrete Hartley transform, International Journal of Computers and Applications, 22(1), 2000, 1–7.
[11] G. Heydt and K. Olejniczak, The Hartley series and its application to power quality assessment, IEEE Transactions on Industry Applications, 29(3), May–June 1993, 522–527.
[12] H. Sorensen, D. Jones, C. Burrus, and M. Heideman, On computing the discrete Hartley transform, IEEE Transactions on Acoustics, Speech and Signal Processing, 33(5), 1985, 1231–1238.
[13] W. Siu and K. Wong, Eﬃcient realisation of discrete Fourier transforms using the recursive discrete Hartley transform, Computers and Digital Techniques, IEE Proceedings E, 136(4), 1989, 254–261.
[14] P.K. Meher, J.K. Satapathy, and G. Panda, New high-speed prime-factor algorithm for discrete Hartley transform, Proceedings of Institute of Electrical Engineering F, Radar and Signal Processing, 140(1), February 1993, 63–70.
[15] G. Bi, New split-radix algorithm for the discrete Hartley transform, IEEE Transactions on Signal Processing, 45(2), 1997, 297–302.
[16] C. Chakrabarti and J. Jaja, Systolic architectures for the computation of the discrete Hartley and discrete cosine transforms based on prime factor decomposition, IEEE Transactions on Computer, 39(11), 1990, 1359–1368.
[17] P.K. Meher, J.K. Satapathy, and G. Panda, Eﬃcient systolic solution for a new prime factor discrete Hartley transform algorithm, Proceedings of Institute of Electrical Engineering G, Circuits Devices and Systems, 140(2), April 1993, 135–139.
[18] P.K. Meher and G. Panda, Novel recursive algorithm and highly compact semisystolic architecture for high throughput computation of 2-D DHT, Electronics Letters, 29(10), May 1993, 883–885.
[19] S.B. Pan and R.H. Park, Uniﬁed systolic array for computation of DCT/DST/DHT, IEEE Trans. Circuits Syst. Video Technol., 7(2), April 1997, 413–419.
[20] P.K. Meher, T. Srikanthan, and J.C. Patra, Scalable and modular memory-based systolic architectures for discrete Hartley transform, IEEE Transactions on Circuits and Systems I: Regular Papers, 53(5), 2006, 1065–1077.
[21] P.K. Meher, J.C. Patra, and M.N.S. Swamy, High-throughput memory-based architecture for DHT using a new convolutional formulation, IEEE Transactions on Circuits and Systems II: Express Briefs, 54(7), 2007, 606–610.
[22] J.-I. Guo, C.M. Liu, and C.-W. Jen, A novel VLSI array design for the discrete Hartley transform using cyclic convolution, Proc. IEEE International Conf. on Acoustics Speech and Signal Processing, 2, Adelaide, Australia, April 1994, II/501–II/504.
[23] J.I. Guo, A new distributed arithmetic algorithm and its hardware architecture for the discrete Hartley transform, Pattern Recognition and Image Analysis, 10(3), 2000, 368–378.
[24] D.F. Chiper, M.N.S. Swamy, and M.O. Ahmad, An eﬃcient systolic array algorithm for the VLSI implementation of a prime-length DHT, 2005 International Symposium on Signals, Circuits and Systems, 1, Romania, July 2005, 167–169.
[25] W.H. Fang and M.L. Wu, Uniﬁed fully-pipelined implementations of one- and two-dimensional real discrete trigonometric transforms, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E82-A(10), 1999, 2219–2230.
[26] A. Amira, An FPGA based parameterisable system for discrete Hartley transforms implementation, Proc. 2003 International Conf. on Image Processing, 2, Spain, September 2003, II–567–70.
[27] P.K. Meher and T. Srikanthan, A scalable and multiplier-less fully-pipelined architecture for VLSI implementation of discrete Hartley transform implementation, IEEE International Symposium on Signals, Circuits and Systems, 2, Romania, July 2003, 393–396.
[28] R. Bracewell, O. Buneman, H. Hao, and J. Villasenor, Fast two-dimensional Hartley transform, Proceedings of the IEEE, 74(9), 1986, 1282–1283.
[29] O. Buneman, Multidimensional Hartley transforms, Proceedings of the IEEE, 75(2), 1987, 267–267.
[30] H. Hao and R. Bracewell, A three-dimensional DFT algorithm using the fast Hartley transform, Proceedings of the IEEE, 75(2), 1987, 264–266.
[31] S. Boussakta and A.G.J. Holt, Fast multidimensional discrete Hartley transform using Fermat number transform, IEE Proceedings ∼ G on Electronic Circuits and Systems, 135(6), December 1988, 253–257.
[32] P.K. Meher, J.K. Satapathy, and G. Panda, Fast computation of multidimensional discrete Hartley transform, Electronics Letters, 28(12), June 1992, 1077–1078.
[33] S. Bouguezel, M. Swamy, and M. Ahmad, Multidimensional vector radix FHT algorithms, IEEE Transactions on Circuits and Systems I: Regular Papers, 53(4), 2006, 905–917.
[34] C.H. Paik and M.D. Fox, Fast Hartley transforms for image processing, IEEE Transactions on Medical Imaging, 7(2), June 1988, 149–153.
[35] R. Bracewell, Aﬃne theorem for the Hartley transform of an image, Proceedings of the IEEE, 82(3), 1994, 388–390.
[36] L. Tao, H.K. Kwan, and J.-J. Gu, Filterbank-based fast parallel algorithms for 2-D DHT-based real-valued discrete Gabor transform, in IEEE International Symposium on Circuits and Systems, Brazil, May 2011, 1512–1515.
[37] L. Tao and H. Kwan, Multirate-based fast parallel algorithms for 2-D DHT-based real-valued discrete Gabor transform, IEEE Transactions on Image Processing, 21(7), 2012, 3306–3311.
[38] A.B. Watson and A. Poirson, Separable two-dimensional discrete Hartley transform, Journal of Optical Society of America, 3(12), 1986, 2001–2004.
[39] M. Perkins, A separable Hartley-like transform in two or more dimensions, Proceedings of the IEEE, 75(8), 1987, 1127–1129.
[40] S. Boussakta and A.G.J. Holt, Prime-factor Hartley and Hartley-like transform calculation using transversal ﬁlter-type structures, in IEE Proceedings G: Circuits, Devices and Systems, 136(5), October 1989, 269–277.
[41] P.K. Meher, T. Srikanthan, J. Gupta, and H.K. Agarwal, Near lossless image compression using lossless Hartley like transform, in Proceedings of the 2003 Joint Conference of the Fourth International Conference on Information, Communications and Signal Processing, 2003 and Fourth Paciﬁc Rim Conference on Multimedia, 1, Singapore, 2003, 213–217.
[42] V.K. Sharma, R. Agrawal, U.C. Pati, and K.K. Mahapatra, 2-D separable discrete Hartley transform architecture for efﬁcient FPGA resource, in 2010 International Conference on Computer and Communication Technology, India, September 2010, 236–241.
[43] K.K. Parhi, VLSI digital signal procesing systems: Design and implementation (New York, NY: John Wiley & Sons, 1999).
[44] P.K. Meher, Highly concurrent reduced-complexity 2-D systolic array for discrete Fourier transform, IEEE Signal Processing Letters, 13(8), 2006, 481–484.
[45] P.K. Meher, Eﬃcient systolic implementation of DFT using a low-complexity convolution-like formulation, IEEE Transactions on Circuits and Systems II: Express Briefs, 53(8), 2006, 702–706.
[46] P.K. Meher, J.C. Patra, and A.P. Vinod, Eﬃcient systolic designs for 1- and 2-dimensional DFT of general transform-lengths for high-speed wireless communication applications, Journal of Signal Processing Systems, 60(1), July 2010, 1–14.
[47] L. Wang, I. Hartimo, and T. Laakso, A novel double-decomposition method for systolic implementation of DFT, Proc. IEEE International Symposium on Circuits and Systems, 3, USA, May 1992, 1085–1088.
[48] C.L. Wang and Y.T. Chang, A novel systolic architecture for the 2-D discrete Fourier transform, Proc. Technical Papers. 1993 International Symposium on VLSI Technology, Systems, and Applications, Taiwan, May 1993, 194–198.
[49] H. Lim and E.E. Swartzlander Jr, Multidimensional systolic arrays for multidimensional DFTs, 1996 IEEE International Conference on Acoustics, Speech, and Signal Processing, 6, USA, May 1996, 3276–3279.
[50] P.K. Meher, LUT optimization for memory-based computation, IEEE Transactions on Circuits and Systems II: Express Briefs, 57(4), 2010, 285–289.
[51] P.K. Meher, Hardware-eﬃcient systolization of DA-based calculation of ﬁnite digital convolution, IEEE Transactions on Circuits and Systems II: Express Briefs, 53(8), 2006, 707–711.
[52] P.K. Meher, New approach to look-up-table design and memory-based realization of ﬁr digital ﬁlter, IEEE Transactions on Circuits and Systems I: Regular Papers, 57(3), 2010, 592–603.
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Abstract
DOI:
10.2316/Journal.202.2013.1.202-3379
From Journal
(202) International Journal of Computers and Applications - 2013
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