DELAY ANALYSIS OF A CMOS BUFFER DRIVEN RLC INTERCONNECT LOAD FOR SUB-THRESHOLD APPLICATIONS

Rohit Dhiman and Rajeevan Chandel

References

  1. [1] S. Hanson, M. Seok, D. Sylvester, and D. Blauw, Nanometer device scaling in sub-threshold circuits, Proc. Design Automation Conference, San Diego, CA, 2007, 700–705.
  2. [2] H. Soeleman, K. Roy, and B. Paul, Sub-domino logic: Ultralow power dynamic sub-threshold digital logic, Proc. 14th International Conference on VLSI Design, Bangalore, India, 2001, 211–214.
  3. [3] H.B. Bakoglu and J.D. Meindl, Optimal interconnection circuits for VLSI, IEEE Transactions on Electron Devices, ED-32 (5), 1985, 903–909.
  4. [4] R. Chandel, S. Sarkar, and R.P. Agarwal, Delay and power management of voltage-scaled repeaters for long interconnects, International Journal of Modelling & Simulation, ACTA Press, 27(4), 2007, 333–339.
  5. [5] Y.I. Ismail and E.G. Friedman, Repeater design to reduce delay and power in resistive interconnect, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 45 (5), 1998, 607–616.
  6. [6] C.Y. Wu and M. Shiau, Accurate speed improvement techniques for RC line and tree interconnections in CMOS VLSI, Proc. IEEE International Symposium on Circuits and Systems, New Orleans, LA, 1990, 2.1648–2.1651.
  7. [7] C.Y. Wu, Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters, IEEE Journal of Solid-State Circuits, 25(5), 1990, 1247–1256.
  8. [8] H. Shichman and D.A. Hodges, Modeling and simulation of insulated gate field-effect transistor switching circuits, IEEE Journal of Solid-State Circuits, SC-3 (3), 1968, 285–289.
  9. [9] M. Nekili and Y. Savaria, Optimal methods of driving interconnections in VLSI circuits, Proc. IEEE International Symposium on Circuits and Systems, San Diego, CA, 1992, 21–23.
  10. [10] A. Morgenshtein, E.G. Friedman, R. Ginosar, and A. Kolodny, Unified logical effort – A method for delay evaluation and minimization in logic paths with RC interconnect, IEEE Transactions on Circuits and Systems, 18(5), 2010, 689–696.
  11. [11] S. Roy and A. Dounavis, Efficient delay and crosstalk modeling of RLC interconnects using delay algebraic equations, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19(2), 2011, 342–346.
  12. [12] G. Antonini, Spectral models for the estimation of delay and cosstalk in high-speed interconnects, IEEE Transactions on Electromagnetic Compatibility, 52(3), 2010, 728–736.
  13. [13] J.A. Davis and J.D. Meindl, Compact distributed RLC interconnect models – Part I: Single line transient, time delay, and overshoot expressions, IEEE Transactions on Electron Devices, 47(11), 2000, 2068–2077.
  14. [14] R. Arunachalam, F. Dartu, and L.T. Pileggi, CMOS gate delay models for general RLC loading, Proc. IEEE International Conference on Computer Design, Austin, TX, 1997, 224–229.
  15. [15] K.T. Tang and E.G. Friedman, Delay and power expression characterizing a CMOS inverter driving an RLC load, Proc. IEEE International Symposium on Circuits and Systems, Geneva, 2002, 283–286.
  16. [16] R. Wang, K. Roy, and C.K. Koh, Short-circuit power analysis of an inverter driving an RLC load, Proc. IEEE International Symposium on Circuits and Systems, Sydney, NSW, Australia, 2001, 886–889.
  17. [17] R. Chandel, S. Sarkar, and R.P. Agarwal, An analysis of interconnect delay minimization by low-voltage repeater insertion, Microelectronics Journal, 38 (4–5), 2007, 649–655. 22
  18. [18] Berkeley Predictive Technology Model (BPTM), 2010. http://www.ptm.asu.edu.
  19. [19] J.M. Rabaey, Analysis and Design of Digital Integrated Circuits – A Design Perspective (TMH, NJ: Prentice-Hall, 2003).
  20. [20] J. Nyathi and B. Bero, Logic circuits operating in the subthreshold voltages, Proc. International Symposium on Low Power Electronics and Design, Tegernsee, Bavaria, Germany, 2006, 131–134.
  21. [21] K. Agarwal, D. Sylvester, and D. Blaauw, Modeling and analysis of crosstalk noise in coupled RLC interconnects, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(5), 2006, 892–901.
  22. [22] D. Sylvester, H. Chenming, O.S. Nakagawa, and O. Soo-Young, Interconnect scaling: signal integrity and performance in future high-speed CMOS designs, Symposium on VLSI Technology Digest of Technical Papers, Honolulu, USA, 1998, 97–98.
  23. [23] B.K. Kaushik, S. Sarkar, R.P. Agarwal, and R.C. Joshi, Crosstalk reduction by voltage scaling in global VLSI Interconnects, Journal of Active and Passive Electronic Devices, 2(3), 2007, 199–221.
  24. [24] D. Bol, R. Ambroise, D. Flander, and J. Legat, Impact of technology scaling on digital subthreshold circuits, IEEE Symposium on VLSI, Monpellier, France, 2008, 179–184.
  25. [25] H. Li, W.Y. Win, and J.F. Mao, Modelling of carbon nanotube interconnects and comparative analysis with Cu interconnects, Proc. Asia-Pacific Microwave Conference, Shanghai, China, 2006, 1361–1364.
  26. [26] S.M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, A Design Perspective (New York: Tata McGraw Hill, 2003).
  27. [27] S. Soleimani, A. Sammak, and B. Forouzandeh, A novel ultralow energy bulk dynamic threshold inverter scheme, Proc. International MultiConference of Engineers and Computer Scientists, Hong Kong, 2009, 1388–1391.

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