Jayanthy Soundararajan and Bhuvaneswari M. Chinnadurai
[1] M. Blyzniuk and I. Kazymyra, Probabilistic-based defect/faultcharacterisation of complex gates from standard cell library,ISSN 1392 – 1215 ELEKTRONIKA IR ELEKTROTECH-NIKA, 3(52), 2004, 67–72. [2] W.Y. Chen, S.K. Gupta, and M.A. Breuer, Test generationin VLSI circuits for crosstalk noise, Proc. IEEE Int. TestConference, 1998, 641–650. [3] W.Y. Chen, S.K. Gupta, and M.A. Breuer, Test generationfor crosstalk-induced delay in integrated circuits, Proc. IEEEInt. Test Conference, 1999, 191–200. [4] W. Chen, S.K. Gupta, and M.A. Breuer, Test generation forcrosstalk induced faults: framework and computational results,Journal of Electronic Testing: Theory and Applications, 18,2002, 17–28. [5] H. Weste and K. Eshraghian, Principles of CMOSVLSI design:a systems perspective, 2nd ed. (Reading, MA: Addison-Wesley,1992). [6] P. Girard, Survey of low-power testing of VLSI circuits, IEEEDesign and Test of Computers, May–June, 2002, 82–92. [7] M. Shakya and S.K.K. Pandian, Low power testing of CMOScircuits: a review, Proceedings of NCSCV’09, 106, 2009. [8] S. Wang and S.K. Gupta, ATPG for heat dissipation minimiza-tion during test application, IEEE Transactions on Computers,47 (2), 1998, 256–262. [9] F. Corno, P. Prinetto, M. Rebaudengo, and M.S. Reorda, A testpattern generation methodology for low power consumption,16th IEEEVLSI Test Symposium, 1998, 453–457. [10] S. Chattopadhyay and N. Choudhary, Genetic algorithm basedapproach for low power combinational circuit testing, 16thIEEE Int. Conf. VLSI Design, 4–8 January 2003, 552–557. [11] H. Takahashi, K.J. Keller, K.T. Le, K.K. Saluja, and Y. Taka-matsu, A method for reducing the target fault list of crosstalkfaults in synchronous sequential circuits, IEEE Transactionson Computer Aided Design of Integrated Circuits and Systems,24(2), 2005, 252–263. [12] E.G. Ulrich, Exclusive simulation of activity in digital networks,Communications of the ACM, 12 (2), 1969, 102–110. [13] K. Deb, Multi-objective optimization using evolutionary algo-rithms (New York: John Wiley and Sons Ltd, 2001). [14] M.C. Bhuvaneswari, S.N. Sivanandam, Genetic algorithmsbased test generation: An analysis of crossover operators,Journal of the Computer Society of India, 32(1), 2002, 10–17. [15] S. Jayanthy, M.C. Bhuvaneswari, Simulation based ATPG forcrosstalk delay faults in VLSI circuits using genetic algorithm,ICGST-Artificial Intelligence and machine Learning Journal,9(2), 2009, 11–17. [16] S. Chary and M.L. Bushnell, Automatic path delay fault testgeneration for combined resistive vias, resistive bridges andcapacitive crosstalk delay faults, Proc. Int. Conf. VLSI Design,Hyderabad, India, 2006. [17] H. Li, P. Shen, and X. Li, Robust test generation for precisecross talk delay faults, Proc. 24th IEEE VLSI Test Symposium,Berkeley, California, USA, 2006. [18] A.D. Sathe and M.L. Bushnell, Analog macromodeling ofcapacitive coupling faults in digital circuit interconnects, Proc.Int. Test Conf., 2002, 375–383.
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