TUNE-UP FRIENDLY FAST SIMULATED ANNEALER FOR VLSI ANALOG MODULE PLACEMENT

Lihong Zhang and Yingtao Jiang

References

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  7. [7] L. Zhang & Y. Jiang, An easy tune-up exponentially fast annealer for high-quality analog module placement, Proc. IEEE Canadian Conference on Electrical and Computer Engineering, 2008, 547–550.
  8. [8] F. Balasa, S. Maruvada, & K. Krishnamoorthy, On the exploration of the solution space in analog placement with symmetry constraints, IEEE Transactions on Computer-Aided Design, 23(2), 2004, 177–191.
  9. [9] L. Ingber, Simulated annealing: Practice versus theory, Mathematical and Computer Modeling, 18(11), 1993, 29–57.
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