VLSI IMPLEMENTATION OF ARTIFICIAL NEURAL NETWORKS – A SURVEY

M. Nirmaladevi and S. Arumugam

References

  1. [1] D. Braendler, T. Hendtlass, & P.O’Donoghue, Deterministic bit-stream digital neurons, IEEE Transactions on Neural Networks, 13(6), 2002, 1514–1525.
  2. [2] T. Aoyama, Learning algorithms for a neural network in FPGA, Proceedings of International Joint Conference on Neural Networks, 2002, I, 1007–1012.
  3. [3] S. Bade & B.L. Hutchings, FPGA based stochastic neural network implementation, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, 1994, 189–198.
  4. [4] K.M. Hornick, M. Stinchcombe, & H. White, Multilayer feedforward neural networks are universal approximators, Neural Networks, 2(5), 1985, 141–154.
  5. [5] M. Marchesi, G. Orlandi, & F. Piazza, Fast neural networks without multipliers, IEEE Transactions on Neural Networks, 4(1), 1993, 53–62.
  6. [6] A. Ferrucci, ACME: A Field Programmable Gate Array Implementation of a Self-adapting and Scalable Connectionist Network, Master’s Thesis, University of California, Santa Cruz, 1994.
  7. [7] N. Takagi, H. Yasuura, & Sh. Yajima, High-speed VLSI multiplication algorithm with redundant binary addition tree, IEEE Transactions on Computers, 34(9), 1995.
  8. [8] B. Hoefflinger, M. Seizer, & F. Warkowshi, Digital logarithmic CMOS multiplier for very high speed signal processing, Proceedings of IEEE Custom Integrated Circuits Conference, San Diego, 1991, 16.7.1–16.7.5.
  9. [9] H. Ossoinig, E. Reisinger, C. Steger, & R. Weiss, Design and FPGA-Implementation of neural network, Proceedings of 7th International Conference Signal Processing Application and Technology, Oct. 1996, 939–943.
  10. [10] J. Chen & W.P. du Plessis, Neural network implementation on A FPGA, Proceedings of IEEE Africon Conf. in Africa, 2002, 337–342.
  11. [11] G.P.K. Economou, E.P. Mariatos, N.M. Economopoulos, D. Lymberopoulos, & C.E. Goutis, FPGA implementation of artificial neural networks: An application on medical expert systems, Proceedings of IEEE International Conference Microelectronics for Neural Networks and Fuzzy Systems, 1994, 287–293.
  12. [12] H. Hikawa, Implementation of simplified multilayer neural networks with on-chip learning, Proc. ICNN, 1995, Nov. 27–Dec. 1, 1633–1637.
  13. [13] A.H. Khan, Multiplier-Free feedforward networks, Proceedings of the International Joint Conference on Neural Networks, 2002, May 12–17, 2698–2703.
  14. [14] Y. Kondo & Y. Sawada, Functional abilities of a stochastic logic neural network, IEEE Transactions on Neural Networks, 3, 1992, 434–443.
  15. [15] M. Gschwind, V. Salapura, & O. Maischberger, Space efficient neural net implementation, ACM Proceedings 2nd International Workshop on FPGA, Feb. 1994.
  16. [16] K. Jayadeva, Recurrent neural networks with nonlinear synapses for solving optimization problems, IETE Journal of Research, 49(2&3), s2003, 197–208.
  17. [17] J.L. Ayala, Design of a pipelined hardware architecture for real-time neural network computations, Proc. 45th Midwest Symposium on Circuits And Systems, Aug. 2002, I: 419–422.
  18. [18] K.Z. Mao, Probabilistic neural network structure determination for pattern classification, IEEE Transactions on Neural Networks, 11(4), 2000, 1009-1016.
  19. [19] N. Aibe, A probabilistic neural network hardware system using a learning parameter parallel architecture, Proc. IJCNN, 3, May 12–17, 2002, 2270–2275.
  20. [20] N. Mehrtash, Synaptic plasticity in spiking neural networks (SP2INN): A system approach, IEEE Transactions on Neural Networks, 14(5), 2003, 980–991.
  21. [21] W. Maass, Networks of spiking neurons: The third generation of neural network models, Proceedings of the Institute for Theoretical Computer Science and Technology, Univ., Austria, 1996.
  22. [22] M. Porrmann, U. Witkowski, & U. Rückert, A massively parallel architecture for self-organizing feature maps, IEEE Transactions on Neural Networks, 14(5), 2003, 1110–1121.
  23. [23] T. Kohonen, Self-organizing maps (Germany: Springer-Verlag, 1995).
  24. [24] T. Schoenauer, S. Atasoy, N. Mehrtash, & H. Klar, NeuroPipechip: A digital neuro-processor for spiking neural networks, IEEE Transactions on Neural Networks, 13(1), 2002, 205–213.
  25. [25] T. Linblad & J.M. Kinser, Image processing using pulse-coupled neural network (Berlin, Germany: Springer Verlag, 1998).
  26. [26] M. Arbib, Background, Handbook of brain theory & neural network (Cambridge, MA: MIT Press, 1995), 879–884.
  27. [27] D. Anguita, A. Boni, & S. Ridella, Digital architecture for support vector machines: Theory, Alg and FPGA implementation, IEEE Transactions on Neural Networks, 14 (5), 2003, 993–1009.
  28. [28] E. Gelenbe, R. Lent, & Z. Xu, Design and analysis of cognitive packet networks, Performance Evaluation, 46, 2001, 155–176.
  29. [29] E. Gelenbe, Z.-H. Mao, & Y.-D. Li, Function approximation with spiked random networks, IEEE Transactions on Neural Networks, 10 (1), 1999, 3–9.
  30. [30] T. Kocak, Design and implementation of a random neural network routing engine, IEEE Transactions on Neural Networks, 14 (5), 2003, 1128–1143.
  31. [31] M. Bracco, S. Ridella, & R. Zunino, Digital implementation of hierarchical vector quantization, IEEE Transactions on Neural Networks, 14 (5), 2003, 1072–1083.
  32. [32] S. Rovetta & R. Zunino, Efficient training of neural gas vector quantizers with analog circuit implementation, IEEE Transactions on Circuits & Systems II, 14, 1999, 688–698.
  33. [33] M. Yagi & T. Shibata, An image representation algorithm compatible with neural-associative processor-based hardware recognition systems, IEEE Transactions on Neural Networks, 14 (5), 2003, 1144–1161.
  34. [34] H. Hikawa, Frequency based MNN with on-chip learning and enhanced neuron characteristics, IEEE Transactions on Neural Networks, 6, 1995, 1109–1118.
  35. [35] Y.C. Kim & M.A. Shanblatt, Architectural and statistical model of a pulse-mode digital multiplayer neural network, IEEE Transactions on Neural Networks, 10, 1995, 545–553.
  36. [36] F.C. Hoppensteadt & E.M. Izhikavich, Pattern recognition via synchronization in Phaselocked-loop neural networks, IEEE Transactions on Neural Networks, 11, 2000, 734–738.
  37. [37] A.F. Murray & A.V. Smith, Asynchronous VLSI NN using pulse-stream arithmetic, IEEE Journal on Solid State Circuits, 23 (3), 1988, 688–697.
  38. [38] Y. Maeda & T. Tada, FPGA implementation of pulse density NN with learning ability using simultaneous perturbation, IEEE Transactions on Neural Networks, 14 (3), 2003, 688–695.
  39. [39] Y. Maeda, A. Nakazawa, & Y. Kanata, Hardware implementation of a pulse-density neural network using simultaneous perturbation learning rule, Analog Integrated Circuits and Signal Processing, 18 (2), 1999, 1–10.
  40. [40] J.E. Tomberg & K.K. Kaski, Pulse-Density modulation technique in VLSI implementation of neural network algorithms, IEEE Journal of Solid State Circuits, 25(5), 1990, 1277–1286.
  41. [41] T. Taniguchi, Y. Horio, & K. Aihara, Integrated pulse neuron circuit for asynchronous pulse neural network, IJCNN, July 20–24, 2003, 2, 942–947.
  42. [42] G. Moon, M.E. Zaghloul, & R.W. Newcomb, VLSI implementation of synaptic weighting and summing in pulse coded neural-type cells, IEEE Transactions on Neural Networks, 3 (3), 1992, 394–403.
  43. [43] J. Babanezhad & G. Temes, A linear NMOS depletion resistor and its application in an integrator amplifier, IEEE Journal on Solid State Circuits, SC-19, 1984, 932–938.
  44. [44] Y. Ota & B.M. Wilamowski, CMOS architecture of synchronous pulse coupled neural network and application to image processing, Proceedings of the IEEE Conf., 2000, 1213–1218.
  45. [45] W. Maass & C.M. Bishop, Pulsed neural networks (London: MIT Press, 1998).
  46. [46] H. Hikawa, A new digital pulse-mode neuron with adjustable activation function, IEEE Transactions on Neural Networks, 14 (1), 2003, 236–242.
  47. [47] H. Hikawa, Learning performance of frequency-modulation digital neural network with on-chip learning, Proceedings IEEE ICNN, 1998, 557–562.
  48. [48] H. Hikawa, A digital hardware pulse-mode neuron with piecewise linear activation function, IEEE Transactions on Neural Networks, 14 (5), 2003, 1028–1037.
  49. [49] H. Hikawa, Pulse mode neuron with leakage integrator and additive random noise, ISCAS 2003, May 25–28, V: 821–824.
  50. [50] H. Hikawa, Hardware pulse-mode neural network with piecewise linear activation function neurons, Proceedings of the IEEE ISCAS, May 2002, II -524–527.–527.

Important Links:

Go Back