Sai P. Kadiyala and Debasis Samanta
Domino logic, favourable gate patterns, pattern recognition, dynamic power dissipation, subgraph matching
Domino logic is often the choice for designing high speed CMOS circuits. Switching of gates in such a CMOS circuit, account for much of its dynamic power dissipation. Power minimization techniques like clock-gating, energy recovery clock, power gating and so on have limitations namely penalty on clock delay, logic overhead, synchronization issues and so on. In this work, we propose a method for implementing clock-gating to a Domino logic-based circuit, using a pattern recognition approach. For a given Domino circuit, first we identify a list of favourable gate patterns (FGPs) that can undergo clock-gating. Next, based on a graph-matching algorithm, we map these FGPs to the circuit elements achieving savings in power and area. Finally, we find an optimum set of patterns so that maximum power savings can be obtained with a minimum penalty on area. We have tested the efficacy of our approach with a set of standard benchmark circuits. Our proposed clock-gating approach offered 15% improvement in power savings and 18% improvement in area penalty compared to the existing work.
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