M.Z. Zhang,∗ H.T. Ngo,∗ A.R. Livingston,∗ and V.K. Asari∗
2-D convolution, symmetric kernel, pipelined architecture, systolic architecture
The design of a high performance digital architecture for computing 2-D convolution, utilizing the quadrant symmetry of the kernels, is proposed in this paper. Pixels in the four quadrants of the kernel region, with respect to an image pixel, are considered simultaneously for computing the partial products of the convolution sum. A novel data handling strategy, to identify pixels to be fed to different processing elements, helps reduce the data storage requirements significantly in the circuitry. The systolic architecture employs parallel and pipelined processing and is able to produce one output every clock cycle. The new design resulted in, approximately, a 75% reduction in number of multipliers and a 50% reduction in the number of adders, when compared to the conventional systolic archi- tecture. The proposed architecture design is capable of performing convolution operations for 57 1,024 × 1,024 frames, or 59.77 million outputs per second, in a Xilinx’s Virtex 2v2000ff896-4 FPGA at maximum clock frequency of 59.77 MHz. The error analysis per- formed in two image processing applications, namely noise filtering and edge detection, shows that the hardware implementation with the proposed design provides results similar to that of the software implementation.
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