Hardware Cache Coherence Protocol

M. Daoui, M. Lalam, B. Djamah, and A. Bilami


Cache coherency, memory consistency, serial multiport memories


This article describes a new hardware cache coherence protocol based on sequential consistency. The protocol uses the directory scheme and invalidation strategy. Two circuits ensure the management of this protocol, one at the processor level and another at each memory bench level, which is organized in serial multiport memory modules.

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