Delay Analysis of a Real-Time Hard Reconfigurable Synchrophasor Synchronization Gateway

Luigi Vanfretti and Prottay M Adhikari

Keywords

Phasor Data Concentrator (PDC), Phasor Measurement Unit (PMU), Synchrophasor Gateway, Wide Area Measurement System (WAMS), Wide Area Control System (WACS), Wide Area Monitoring Protection and Control (WAMPAC)

Abstract

Phasor Data Concentrators (PDC) receive and time-synchronize phasor data from multiple phasor measurement units (PMUs) to produce a real-time, time-aligned output data stream. PDCs are expected to handle large sets of data and may consume substantial hardware resources in terms of memory. This paper presents some preliminary results towards the development of a hard real-time storageless Synchrophasor Gateway based on National Instruments' Compact Reconfigurable Input-Output (cRIO) hardware platform. It utilizes the Khorjin library [1] which is able to receive and parse synchrophasor data from a PMU/PDC based on IEEE C37.118.2 protocol. A fully functional PDC is expected to store and publish PMU data. The proposed real-time hardware prototype, however does not store data, as its goal is to provide essential synchronization and aggregation functions to be used by protection and control devices. Hence, this prototype is described as a Synchrophasor Synchronization Gateway (SSG) instead of a PDC. In this paper, elementary tests related to timing, delay and reliability are performed on the SSG, and the results along with the observed issues are reported.

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