Go Matsumura, Michihiro Koibuchi, Hideharu Amano, and Hiroki Matsutani
Network-on-Chip, Chip Multi-Processor, Wireless 3D IC, Bus
Because of the increase in cost for chip fabrication, designing a chip family in accordance with the application is becoming an expensive choice. Wireless 3D IC design offers flexibility to connect known-good-dies selected after chip fabrication. It can stack an arbitrary number of chips at low cost. In this paper, dynamic time division multiple access (D-TDMA) is used for vertical broadcast buses for high communication efficiency of interchip network. However, to implement simple D-TDMA based 3D IC, large area and energy overheads are needed for arbitration since another inductor is needed for sending just several bits as arbitration signal in addition to an inductor for the data transfer. We resolve this problem to employ a carrier sense multiple access with collision detection (CSMA/CD) for arbitration of D-TDMA vertical broadcast buses. Evaluation results show that the proposed bus architecture reduces the number of inductors by 73.6% compared to a simple counterpart which employs D-TDMA based 3D buses. The results also show that an application execution time increases only by 0.3% at most.
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