Design and Simulating a Specialized Embedded Cores for UDP Network Interface Processing

Mohamed Elbeshti, Mike Dixon, and Terry Koziniec


Large Receive Offload, RISC Core, TCP/IP, VHDL Simulator, Cycle-Accurate Performance Evaluations, Network Interfaces


The speed of Ethernet networks has increased to 40- 100 Gbps since the release of IEEE P802.3ba. Enhancing the protocol processing at the end node is essential to meet the demands of the increased network speeds. This research presents an enhanced pre-packet processing for inbound and outbound processing using a scalable Network Interface-based three-pipeline Embedded Processor. The designed Network Interfaces uses a specialized cost-effective 760 MHz embedded processor core can support a wide range of received UDP/IP packets, up to 100 Gbps. A 430 MHz Embedded Processor can be used for the send side. Furthermore, we have provided a processing methodology for Large Receive Offload and Large Send Offload that can contribute to pre-packet processing and work with fewer headers and data transfer from the network interface.

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