Chi-Shan Yu and Jun-Zhe Yang
Phasor measurement unit, phase lock loop, discrete Fourier transform, Android
Phasor measurement units (PMUs) have recently been widely studied for smart grid power systems. However, the setup time of a PMU is slow because a conventional phase lock loop (PLL) needs a long settling time to synchronize its first trigger pulse for measuring a synchrophasor. In addition, the user interface of a PMU is poor because most of PMUs have no GUI design. This current work thus presents a new Android-based PMU, which contains a new digital phase lock loop (DPLL) and versatile user interfaces. Using the proposed DPLL, the time synchronous trigger pulses can be rapidly generated from the 1PPS pulses. An Android platform is then designed to receive the time synchronous measurements. To accelerate phasor computations, the discrete Fourier transform (DFT) was directly coded by C language and communicate with Java codes by the Java native interface (JNI). Finally, the proposed PMU was realized on a test system which consists of a DE2 FPGA board, a PIC board, and an ARM-11 6410 board. A simple user interface was also designed on the Android platform for setting and observing some features of the PMU. Hardware evaluations were conducted to prove the effectiveness of the proposed PMU.
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