Nopphol Noikaew and Orachat Chitsobhuk
MQ-Coder, Arithmetic Encoder, JPEG2000, Hardware Architecture, FPGA Implementation
The key algorithm in JPEG2000 image compression system is embedded block coding with optimized truncation (EBCOT). The EBCOT scheme consists of a bit-plane coder coupled with a MQ arithmetic coder. Recently, the bit-plane coding can generate more than one symbol per clock cycle. Consequently, the coding speed is limited and bottlenecked at the interface between the output of the bit-plane coding and the input of the MQ arithmetic coder. Moreover, an efficient designed architecture for MQ arithmetic coder should compromise between processing speed and hardware cost. Therefore, a single symbol processor for arithmetic coder architecture implemented on FPGA is proposed in this paper, since it offers high throughput but requires low hardware cost. The proposed architecture is separated into 2 pipelined stages to break down the whole task into smaller sub-tasks, which leads to great reduction in the critical path. Consequently, it demonstrates no stall, high clock speed and high throughput in the encoding process. These benefits are achieved with the suitable hardware design, pipelining technique, pre-calculation, and prediction process. As a result, the coding speed can be at least 188.99 MHz with the throughput of 188.99 MCxD/S.
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