Evaluation of Architectural Supports for Fine-Grained Synchronization Mechanisms

Tiziano De Matteis, Fabio Luporini, Gabriele Mencagli, and Marco Vanneschi


Synchronization, Locking, Simultaneous Multi-Threading, Busy-Waiting


The advent of multi-/many-core architectures demands ef- ficient run-time supports to sustain parallel applications scalability. Synchronization mechanisms should be op- timized in order to account for different scenarios, such as the interaction between threads executed on different cores as well as intra-core synchronization, i.e. involving threads executed on hardware contexts of the same core. In this perspective, we describe the design issues of two notable mechanisms for shared-memory parallel computa- tions. We point out how specific architectural supports, like hardware cache coherence and core-to-core interconnec- tion networks, make it possible to design optimized imple- mentations of such mechanisms. In this paper we discuss experimental results on three representative architectures: a flagship Intel multi-core and two interesting network pro- cessors. The final result helps to untangle the complex im- plementation space of synchronization mechanisms.

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