Selvaraj George
Network on Chip, SOC, FPGA, Router, VLSI Design, Embedded Systems
Present day technology for ASICs supports Networks-on-Chip designs which can have 100 million gates on a single chip. The latest FPGAs can support only about 10 million gates to accommodate all logic and the associated routings. In order to implement competitive Networks on Chip (NoC) architecture in FPGA’s, the occupancy by the networks should be kept minimum. This ensures that the maximum area can be utilized by the logic while maintaining the performance of router networks. Reducing the area also reduces the power consumption. In this paper we report an implementation of a parallel router which can support five simultaneous routing requests. We introduce optimizations in XY routing and decoding logic thereby gaining in area and performance. The header overhead is 8 bits per packet and the packet size can vary between 16 and 128 bits
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