Pawandeep Kaur, Jyotirmoy Pathak, and Gurwinder S. Cheema
Parallel Multiplier, VLSI Design, Low Power Design
In this paper, we present the design of a low-power and efficient parallel multiplication unit. This multiplier architecture is based on Jin-Tai Yan bypassing based multiplier. In order to improve his architecture, the activity for generating control signal is reduced and thereby also reduction of power consumption is achieved. The area overhead is reduce by the 14.3% whereas the reduction in switching power consumption is 20.4 %, thereby improving the efficiency of this multiplier with dip of 9.01% in terms of PDP
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