Rajkumar Sarma and Jyotirmoy Pathak
PTL, GDI, PDP, Low Power, Full Adder, VLSI
Adder cell using Pass Transistor Logic (PTL) and Gate Diffusion Technique (GDI) is been described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented. In this paper, we propose a new PTL-GDI based cell designs, which is found to be much more power efficient in comparison with existing design technique. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180nm environment
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