Safety Analysis Method based on a Parallel State Transition Diagram for Embedded Systems

Zoohaye Kim, Yutaka Matsubara, and Hiroaki Takada


State Transition Diagram, Safety Analysis, UML, HAZOP, SHARD


In order to exhaustively analyze the effects of failures in safety-critical embedded systems, we have studied safety analysis methods based on state transition diagrams. However, the analytical worksheets and guidewords used in these methods are not suitable for analyzing parallel state transition diagrams, which represent the behavior of systems whose functions work in parallel. We propose a method whereby, if the severity of a deviation on a state transition diagram can be determined regardless of the other state transition diagrams, the total number of deviations to be analyzed can be reduced. Moreover, we show that techniques for containing the effects of deviations (e.g., memory protection) can limit their analytical area. Thus, we perform a Safety Analysis method based on a Parallel State Transition Diagram (SAPSTD). To clarify its effectiveness, we apply a conventional method and SAPSTD to the specifications of an example embedded system and compare the results of an evaluation.

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