Implement and Evaluation of a Multi-Core FPGA Calculation Device on a Smart Hetero-Cluster

Shinji Kawasaki and Kiyoshi Hayakawa

Keywords

Heterogeneous Computing, FPGA, MultiCore Processing, Low–Power Consumption

Abstract

Recently, general-purpose processors have made the transition from high-frequency single cores to multiple cores as a consequence of multi-core processors requiring less power. To further reduce power consumption, it is necessary for field-programmable gate arrays (FPGAs) to embed multi-core processors. For smart cluster systems, it is important to reduce CO2. Therefore, it is necessary for smart cluster systems to change dynamically the number of compute nodes including FPGAs as determined by the power consumption of the entire facility in order to reduce the total power consumption of the cluster system and other electronic devices. In this paper, we design a multi-core processor which processor is embedded into Smart PC HeteroCluster (SPHC). The processor in the FPGA is designed using ASIP Meister. In the performance evaluations, we achieved a speed increase with eight cores of 7.8 times over that of a single core. The power consumption of eight cores is 2.58 times higher than that of a single core.

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