Performance Analysis of Different Multiplication Strategies in Reconfigurable Hardware

Umer N. Misgar and Muhammad Hasan

Keywords

ReConfigurable Architecture, Power Aware Systems, Carry Ripple, Carry Save

Abstract

A multiplier is one of the key hardware blocks in most high performance systems such as FIR filters and DSP’s. The performance of these systems is significantly influenced by the speed of the multipliers they utilise. An application may need different optimized hardware (either for power or for speed) at different time. A reconfigurable platform can accommodate such requirements. This paper compares two broad schemes of combinatorial multipliers implemented using adders in reconfigurable hardware. Furthermore, the paper looks into applying the above mentioned strategies in two different platforms to compare the variations in power, area and speed. The multiplier implemented with carry save adder in parallel showed better performance than the others. At minimum, the above configuration shows 13% delay improvement as well as 18% power efficiency than the other multipliers. However, this gain is achieved at an expense of 13% more hardware. All simulations are carried out on a Xilinx Spartan 3E and Altera’s EP2S15F484C3 FPGA using VHDL.

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