Kefei Wang, Heyin Zhang, and Ming Fang
Switch, Crossbar, Throughput, HPC, TILE
Research and trends reveal that high-radix switch is a necessity in future HPC design. HOL blocking limits the throughput of an N×N crossbar to less than 58% and this can be even worse in high radix switches. In this paper, a new efficient architecture for high-radix switches is proposed. The architecture, re¬ferred to as Hierarchical Asymmetric Crossbar (HAC), re¬lies on the fact that in an asymmetric crossbar, where input ports are much less than output ports, effect of HOL blocking on crossbar throughput is very samll or negligible. Thus an HAC architecture of N×N high radix switch can be formed by N/m smaller m×N asymmetric crossbars to achieve high throughput without any special endeavours to eliminate HOL blocking. A prototype of 32×32 HAC high radix switch is introduced in the paper. Clock cycle simulation reveals that in such a switch the impact of HOL blocking is almost thoroughly eliminated and the switch throughput can be as high as 94%. The HAC based switch can be implemented in TILE-based array structure to simplify the switch design.
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