EFFICIENT SYSTOLIC ARCHITECTURE FOR VLSI REALIZATION OF 2-D HARTLEY-LIKE TRANSFORM

Gouri S. Maharana, Pramod K. Meher, and Basant K. Mohanty

Keywords

Discrete Hartley transform, multidimensional DHT, separable DHT, Hartleylike transform

Abstract

In this paper, we present a composite systolic structure for VLSI realization of two-dimensional (2-D) separable Hartley-like transform (HLT). We have shown that using the separable nature of 2-D HLT, one can compute it in two pipeline stages by row–column decomposition. Besides, we have presented two linear systolic structures for the computation of those two stages and shown that both the types of linear systolic structures can be orthogonally interspersed together to derive a composite structure for 2-D HLT, which does not require any of transposition buffer. The proposed structure provides two benefits: Neither does it require any on-chip memory for transposition of intermediate matrices nor it involves any delay to perform transposition operation. The proposed design for N × N HLT provides a throughput-rate of N HLT coefficients in every cycle, since row and column processing could be performed concurrently for adjacent pairs of input matrices. Unlike the 2-D discrete Fourier transform (DFT) structures, the proposed structure does not require any complex arithmetic operations. It is comprised of 2N2 locally connected simple processing elements (PEs), where each PE consists of one real-value multiplier and one real-value adder. The complete structure, therefore, involves 2N2 multipliers and the same number of adders, while the 2-D DFT of the same size requires 8N2 multipliers and 8N2 adders.

Important Links:



Go Back