Ritesh Parikh and Santanu Chattopadhyay
AND-XOR, area-power trade-off, Reed–Muller, power reduction, logic synthesis
Logic minimization based on AND-OR decomposition of functions is a well-studied area. However, minimization, particularly power- aware technique, based on AND-XOR decomposition has received relatively lesser attention. This paper presents a multi-level AND- XOR network synthesizer that incorporates area-power trade-off in the decision-making process. The synthesizer can produce circuits consuming 23.77% less switching power and 9.53% less leakage power, on an average, over synthesis approaches targeting area minimization.
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