S.R. Das (Canada, USA), S. Mukherjee (Canada), S.N. Biswas (USA), A. Hossain, and E.M. Petriu (Canada)
Built-in self-test (BIST), fault grading, fault simulation,ISCAS benchmark circuits, Paul-Unger method, systemon-chips (SOCs).
The design of space-efficient support hardware for built in self-testing (BIST) is of major significance in the realization of embedded cores-based system-on-chips (SOCs). The subject paper reports on further studies on a new space compression technique that facilitates designing such circuits using pseudorandom and compact test sets, with the primary objective of minimizing the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information. The proposed compaction technique utilizes the concept of fault graded output merger based on the information of strong and simply compatibles pairs of response data outputs of the CUT. The approach developed herein guarantees simple design with 100% fault coverage for single stuck-line faults, low CPU simulation time and acceptable area overhead. Simulation runs on ISCAS 85 combinational and ISCAS 89 full scan sequential benchmark circuits with simulation programs FSIM and ATALANTA confirm the usefulness of the suggested methodology.
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